The present invention relates to data processing, and more particularly, to a method of performing operations with a variable arithmetic within a data processing system.
Operators which can perform operations from operands of which the number of bits can vary are said to be of variable arithmetic. For instance, an adder which can carry out additions between operands coded on 16 bits or between operands coded on 24 bits is said to be of dual arithmetic: it is compatible with both a 16-bit arithmetic and a 24-bit arithmetic.
Special processors known as digital signal processors (DSPs) are designed specially for digital signal processing. DSPs are more particularly used for functions specific to processing digital signals, such as filtering or signal comparison. In some data processing systems, a DSP can be associated to a more powerful host processor to perform complex signal processing functions.
Some operations such as multiplication with accumulation are classical operations performed by DSPs: these operations involve multiplying together two binary numbers and adding, as the case arises, a third binary number to the result of that multiplication. In some digital signal processing algorithms used e.g. for carrying out Fourier transform calculations or for modeling finite impulse response filters or infinite impulse response filters, DSPs are excellent for multiplication operations with accumulation.
Some applications require great attention and precision especially for carrying out arithmetic operations. For instance, reproducing a high-fidelity sound can call upon calculations that bring into play numbers coded on more bits than required for calculations in simple voice transmissions. The increase in the number of bits involved in calculations leads to a greater degree of precision.
Conversely, there are other operations that call upon operations requiring calculations which involve numbers coded on a precise number of bits; for that type of operation, the possibility of working with numbers providing a better precision by virtue of a greater number of bits is not adopted. Sometimes, this possibility is even excluded for these operations. For instance, there exist communications standards in cellular telecommunication systems, such as the GSM standard in Europe, which impose numbers coded on 16 bits only, and which do not accept numbers coded on more than 16 bits even if that makes it possible to attain greater precision. On the other hand, numerous and recent multimedia applications dedicated to digital signal processing now demand a high degree of precision, especially for reproducing audio signals, all while being able to conform to the GSM standard in order to receive telecommunications that comply to that standard.
There thus arises the following problem: powerful operators, i.e. those working with numbers coded on a large number of bits, and less powerful operators, which must work with numbers coded on a number of bits imposed by certain standards, must coexist. Today, it is no longer possible to make a choice between these two types of operators, and hence between two different arithmetics. A solution would be to have two groups of distinct operators coexisting within the DSPs, each of the two groups operating with a different arithmetic. However, such a solution is penalizing in terms of cost and circuit space.
Moreover, there are some problems caused by the use of multiple arithmetic systems. Indeed, in the case where an operation is performed between two k-bit numbers, the result may take up k+1 bits. For operations performed with a single arithmetic, the k lowest weight bits are written into a result register. The last bit, which is the most significant bit, is called the outgoing carry over bit. For some applications, the presence of an outgoing carry over bit in the result of a given operation indicates that a saturation value has been attained and that, as a consequence, the result contained in the result register is no longer taken into account. It is thus important that the outgoing carry over bit is not written into the result register.
FIGS. 1a, 1b and 1c illustrate the problem that can arise. In FIG. 1a, an adder 1 performs an addition between a first 4-bit number of value 1010 stored in a first 4-bit input register 2, and a second 4-bit number of value 0100 stored in a second 4-bit register 3. The result of the addition, i.e. the number 1110, is contained in a result register 4. There is no outgoing carry over bit.
In FIG. 1b, the adder 1 performs an addition between a first 4-bit number of value 1010 stored in the first 4-bit input register 2 and a second 4-bit number of value 0111 stored in the second 4-bit input register 3. The result of the addition is 10001. This number is thus coded on five bits. The four lowest weight bits of that result are contained in the result register 4. The fifth bit corresponds to an outgoing carry over bit 5. Its presence activates a saturation unit within the electronic circuit managing the addition.
Thus, for example, if the result of the addition determines the sound volume level, a predetermined maximum amount shall be outputted. The four lowest weight bits of the result are then no longer taken into account. Likewise, there can exist a minimum predetermined value in the case where the result of an operation generates an outgoing carry over bit indicating a result which is less than what can be coded on a set number of bits.
In FIG. 1c, the adder 1 performs an addition between a first 2-bit number of value 10 stored in the first 4-bit input register 2, and a second 2-bit number of value 11 stored in the second 4-bit input register 3. The result of the addition is 101. This number is thus coded on three bits, all three bits being contained in the 4-bit result register. Now this addition was an addition performed in accordance with a 2-bit arithmetic using a 4-bit adder. Accordingly, the most significant bit of the result which, according to 2-bit arithmetic, should be the outgoing carry over bit, is kept in the result register. As a consequence, no saturation unit is activated.
These simple illustrations serve to show the possible existence of an outgoing carry over and the role it can play, as well as the problem arising from the use of a double arithmetic for recovering the outgoing carry over.
U.S. Pat. No. 5,598,362 proposes a method which implements a double arithmetic with a unique set of operators. In this patent, operations calling into play numbers coded on 16 bits or on 24 bits are performed with the same operators. However, the proposed solution requires an alignment of numbers prior to the operation. Thus, for instance, if two 4-bit numbers are to be added using an adder initially intended for adding numbers coded on 8 bits, it is necessary to abide by a set of steps shown in FIGS. 2a to 2d, which correspond to the following events:
in FIG. 2a, storing a first 4-bit number of value 1010 in a first 8-bit input register 6 and storing a second 4-bit number of value 0111 in a second 8-bit input register 7;
in FIG. 2b, shifting the first 4-bit number towards the most significant bits of the first 8-bit input shift register 6, and shifting the second 4-bit number towards the most significant bits of the second 8-bit input shift register 7;
in FIG. 2c, performing the addition using an 8-bit adder 8 and storing the obtained result of value 10001 in a result register 9; an outgoing carry over 10 is obtained in this example;
in FIG. 2d, shifting the 4 most significant bits of the obtained result towards the least significant bits of an 8-bit result register 9 which contains the result of the addition.
There is thus obtained the result of the addition of two 4-bit numbers performed with an 8-bit adder. The different shift operations are necessary to recover a possible outgoing carry over 10 which can thus be interpreted upon performing an addition. The outgoing carry over is sent to a saturation unit which enables a correct result to be obtained.
However, all these shift operations necessary to carry out the simplest of operations are very costly in terms of the execution time for the operation.
The method according to the invention makes it possible to overcome the different faults and drawbacks described above.
The invention relates to a process for implementing a double arithmetic: operators initially intended for performing operations on n-bit numbers can be utilized, by virtue of the inventive method, for performing those same operations on k bits, where n and k are natural integers such that k is less than or equal to n.
The method according to the invention implements means for performing operations with a variable arithmetic which require no shift operation for the input data of the operator. For example, to perform an addition of two numbers coded on 4 bits using an 8-bit adder, it is not necessary to shift the 4 bits of the two numbers towards the most significant bits of input registers of the operator. The result of the addition obtained is besides written directly in the lowest weight bits of the register containing the addition. Moreover, the method according to the invention implements means to recover a possible carry over which can activate a saturation unit of the DSP.
The invention thus relates to a method of performing operations with a variable arithmetic within a data processing system, including the steps of:
storing a first operand of k bits in a first input register of n bits;
storing a second operand of k bits in a second input register of n bits;
completing the n-k bits of each input register with sequences of bits ensuring, in a result register containing the result of the operation, a propagation of a possible outgoing carry over bit to recover the outgoing carry over at an output of the result register; and
executing the operation.
According to a preferred embodiment of the invention, the sequences of bits ensuring the propagation of a possible outgoing carry over bit are specific to each operator. These sequences can also be representative of the arithmetic according to which the operation is executed.
According to a particular embodiment of the method according to the invention, the n-k highest weight bits of the result register containing the result of the operation are set to zero.